Field
The embodiments are generally directed to die stacking technology. More particularly, the embodiments are directed to a processor with host and slave operating modes stacked with memory.
Background Art
3-D die-stacking technology enables logic dies and memory dies to be stacked in a manner that enables high-bandwidth, low-latency access to the memory from the logic die stacked with it. Such technology presents opportunities for performing computations close to the memory. However, current mainstream memory designs do not implement any computation capability in memory dies as the memory implementation processes are inefficient for logic. Current implementations are aimed at either limited logic capability in the memory stack operating under the control of a host processor or processor designs that operate independently out of the stacked memory. Both of these solutions can be improved upon.